As the demand to push semiconductor device features deeper into the sub-micron range has increased, numerous techniques have been developed for increasing the performance and circuit density of Static Random Access Memories (SRAMs), while also minimizing power dissipation. Most SRAM cells are implemented as cross-coupled inverters, which, in contrast to Dynamic Random Access Memories (DRAMs), do not require periodic refreshing in order to preserve the stored data as long as circuit power is maintained. Primarly, each of the cross-coupled inverters usually consist of an active transistor and a load resistor. For full CMOS SRAMs, the active transistor is usually an N channel device and the effective load resistor is usually a P channel device. For MOS SRAMs. the active transistor is usually an N channel device and the load resistor is usually formed from high resistivity polysilicon. For typical SRAM cells, the above examples of cross-coupled inverters are used for information storage and two additional transistors are used for writing and reading information to and from the cells. Consequently, depending on the type of load resistor that is used, an SRAM cell can be comprised of 4 or 6 transistors. Choosing a particular SRAM technology for a given application involves numerous considerations. For minimal low standby power, full CMOS SRAM implementations are usually preferred. However, for simplicity, small cell size, low process cost and good speed performance, MOS implementations, such as NMOS, are often preferred.
NMOS SRAMs, using polysilicon load resistors, can be implemented on large single P wells. while minimizing cell size and process complexity that would, otherwise, be needed to electrically isolate N and P channel devices. This has led to considerable popularity of four transistor, NMOS, SRAM (4T SRAM) technology. Although 4T SRAMs offer a number of attractive features, techniques for managing the evolving trade-offs between some cell failure concerns and excessive power dissipation have been a challenge. While lower SRAM operating currents are desirable for minimizing power dissipation, there are constraints on how low the operating currents can be. For example, SRAM cell failures can occur if excessive leakage currents become comparable to the on-state currents of the cell. In addition, the stored capacitive charge in the cell needs to be sufficient for protection from soft error failures, due to alpha particles. This, in turn, dictates that the operating currents of the cell be high enough to still allow for rapidly switching the memory state of the cell. Due, in part, to some of the above considerations between cell failures and excessive power dissipation, SRAMs have tended to use some evolving optimum value of cell operating current, while employing a number of techniques to maintain the operating current in a fairly constant optimal range. For 4T SRAMs, undesirable variations in optimal operating current are usually due to variations in the polysilicon load resistors, where the temperature coefficient of resistance, TCR, is often of great concern. Polysilicon resistors tend to exhibit rather large negative TCR values, which can lead to the problem of insufficient cell operating currents at low temperatures, for example.
Polysilion resistors, as a controlling factor of SRAM operating currents, have been the subject of considerable attention.
U.S. Pat. No. 4,579,600 to Shah, et. al., teaches a method for using a two step process to reduce the large thermally activated grain boundary contribution to polysilicon sheet resistance that is typically responsible for a high negative TCR. A short high temperature annealing step is used to increase grain size and, thereby, reduce the number of grain boundaries as well as to reduce charge trapping at the grain boundaries. An additional step is taught for incorporating ionic hydrogen in the grain boundaries, as a means of achieving a further reduction of grain boundary trap density. By minimizing the grain boundary contribution to a negative TCR, the positive TCR contribution from the bulk of the grains is, therefore, able to be relatively more significant. Consequently, proper adjustment of the above extra process steps can be used to achieve a near zero TCR value. While addressing the problem of high negative TCR's of polysilicon resistors, the time and expense for additional process steps may not always be compatible with manufacturing needs for an SRAM process.
U.S. Pat. No. 4,622,856 to Binder, et. al., teaches a method for obtaining precise polysilicon resistors, with low TCR values. High doping of the polysilicon is used to reduce the negative TCR contributed by the polysilicon grain boundaries, relative to the positive contribution to TCR from the bulk of the grains. Precision tailoring of the resultant polysilicon resistors is accomplished by laser trimming. However, the high level of polysilicon doping that is needed for reducing the negative TCR does not seem to be compatible with the need for very high valued polysilicon, SRAM. load resistors in the sub-gigaohm to high gigaohm range.
U.S. Pat. No. 4.579,600 to Bourassa, et. al., teaches a method for obtaining high valued polysilicon resistors, while minimizing an otherwise high negative TCR due to thermally activated grain boundaries. An additional masked ion implantation step is used to convert each polysilion resistor line into two lateral disposed back-to-back PN junctions. The effective series resistance of the back-to-back diodes exhibits a much lower negative TCR than that of a uniformly doped polysilicon line with a comparable nominal resistor value. However, part of the cost for this benefit is an extra masking step and a minimum polysilicon resistor line length restriction for accommodating the photolithography ground rules associated with the additional masked, opposite conductivity, ion implant step.
U.S. Pat. No. 5,489,547 to Erdeljac, et. al., teaches a method for obtaining polysilicon resistors with moderate sheet resistance values and reduced values of negative TCR. An additional opposite conductivity ion implantation step is used to counter dope a previously ion implanted polysilicon resistor. The invention features the counter doping approach as a means of obtaining moderate polysilicon sheet resistance values without the need for additional process steps. However, such moderate values of sheet resistance do not seem to be compatible with the need for high polysilicon load resistors in the low-high gigaohm range, for 4T SRAMs.
There remains a need for a solution to the problem of reducing the negative TCR of polysilicon resistors and by means of a method that adds very little additional cost or time to a conventional 4T SRAM process, for example. The present invention solves this problem by forming a shallow vertical PN junction between the surface and sub-surface of the entire length of a polysilicon resistor. It is believed that the resultant space charge region (SCR) of the PN junction tends to adjust the effective electrical thickness of the polysilicon resistor, such as to make it thicker at colder temperatures. The effect of the changing SCR width with temperature helps to compensate the tendency for the thermally activated barrier of the grain boundaries to increase polysilicon sheet resistance at colder temperatures. This is accomplished by using an ion implantation process to form a shallow P type layer on the surface of a uniformly doped N type polysilicon resistor.